MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk
Proceedings of the International Workshop on Smalltalk Technologies
Leveraging reconfigurability to raise productivity in FPGA functional debug
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a new debugging methodology for applications targeting reconfigurable platforms. The key issue behind is that bringing software engineering techniques advantages to hardware design would reduce design cycles hence time-to-market. Our high-level synthesis framework supports probes insertion both in the behavioural description of the application and in its hierarchical netlist. Probe status can control the execution, and traced signals can be read back from software. Probes' conditions can be reassigned at runtime tackling the main disadvantage of modifications through re-synthesis and favours short debugging cycles similarly to software development.