A security scheme for dependable key insertion in mobile embedded devices
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
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A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2n-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Exploiting the features of the MicroBlaze's integrated interfaces instructions are streamed on-demand to the coprocessor to keep the controlflow highly flexible. At the same time the dataflow between hardware and software is minimized. Comparison with previous architectures shows high acceleration of HECC with minor increase in hardware resources. It is demonstrated that this speed-up can be used for countermeasures on algorithmic level against basic side-channel attacks while still keeping real-time constraints.