An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

Authors:
Taecheol Oh;Hyunjin Lee;Kiyeon Lee;Sangyeun Cho
Affiliations:
-;-;-;-
Venue:
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Year:
2009

Citing 0
Cited 2

Scale-out processors

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Parallel Computing

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Abstract

The Scalable Communications Core (SCC) is a flexible baseband processor that consists of a heterogeneous set of coarse-grained, programmable accelerators connected via a packet-based 3-ary 2-cube Network-on-Chip (NoC). SCC supports multiple wireless ...