Packet-level static timing analysis for NoCs

  • Authors:

  • Evgeni Krimer;Mattan Erez;Isaac Keslassy;Avinoam Kolodny;Isask'har Walter

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Texas at Austin, USA;Department of Electrical and Computer Engineering, University of Texas at Austin, USA;Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel;Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel;Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel

  • Venue:
  • NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
  • Year:
  • 2009

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Abstract

Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of these highly-integrated systems. Towards this modeling goal, we present a methodology for packet-level static timing analysis in NoCs. Our methodology enables quick and accurate gauging of the performance parameters of a virtual-channel wormhole NoC without using simulation techniques and supports any topology, link capacities, and buffer depths. It provides per-flow analysis that is orders-of-magnitude faster than simulation while being both significantly more accurate and more complete than prior static modeling techniques. Our methodology is inspired by models of industrial flow-lines. Using a carefully derived and reduced Markov chain, the model can statically represent the dynamic network state and closely estimate the average latency of each flow. Use of the model in a placement optimization problem is shown as an example application of the method.