Architecture for dense matrix multiplication on a high-performance reconfigurable system

  • Authors:
  • Viviane L. S. de Souza;Victor W. C. de Medeiros;Manoel E. de Lima

  • Affiliations:
  • Federal University of Pernambuco, Recife-PE, Brasil;Federal University of Pernambuco, Recife-PE, Brasil;Federal University of Pernambuco, Recife-PE, Brasil

  • Venue:
  • Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
  • Year:
  • 2009

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Abstract

The recent evolution of the programmable logic devices, such as FPGAs (Field Programmable Gate Array), associated with the growing demand for performance improvements in scientific computing applications, has attracted the attention of supercomputers vendors. They have been developing hybrid platforms that links general-purpose processors with co-processors based on FPGAs, aiming computing acceleration. In this work we present the analysis and development of an important scientific computing operation: matrix multiplication, targeting the commercial hybrid platform RASC (Reconfigurable Application-Specific Computing), developed by Silicon Graphics. The proposed architecture aims to reach better performance than conventional architectures, dissipating less power. To achieve this goal, we investigated the possibilities of implementation in parallel and data reuse intrinsic to the algorithm. Based on this investigation we propose a case study that uses the available resources in the target platform to explore these features.