Using MDE for the formal verification of embedded systems modeled by UML sequence diagrams

  • Authors:

  • Francisco Assis M. do Nascimento;Marcio F. da Silva Oliveira;Flávio R. Wagner

  • Affiliations:

  • Federal University of Rio Grande do Sul, Porto Alegre - RS - Brazil;Federal University of Rio Grande do Sul, Porto Alegre - RS - Brazil;Federal University of Rio Grande do Sul, Porto Alegre - RS - Brazil

  • Venue:
  • Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
  • Year:
  • 2009

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Abstract

This work presents a formal verification methodology that adopts concepts from Model Driven Engineering (MDE) for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By means of transformations on the UML model of the embedded system, a MOF-based representation for the network of timed automata is automatically obtained, which can be used as input to model checking tools, as Uppaal, in order to validate desired functional and temporal properties of the embedded system specification. Since the network of timed automata is automatically generated, the methodology can be very useful for the designer, making easier the debugging and formal validation of the system specification. The paper describes the defined transformations between models, which generate the network of timed automata as well as the textual input to the Uppaal model checker, and illustrates the use of the methodology with a case study to show the effectiveness of the approach.