Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream
IEEE Transactions on Computers
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It is desirable to achieve high read bandwidths for the processing elements of highly concurrent SISD computers, both while keeping the register and memory write bandwidths low, and while keeping the interconnection networks simple. Solutions to these problems are proposed, simulated, verified, and measured. New techniques called write elimination and write liberation are presented that also greatly reduce the complexity of the data cache. The elimination of addressable hardware registers is also achieved.