DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Considering the effect of process variations during the ISA extension design flow
Microprocessors & Microsystems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Editor's note:CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area.—Philippe Coussy, Université de Bretagne-Sud