VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware

Authors:
Sheng-Kai Weng;Chien-Min Ou;Wen-Jyi Hwang
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117;Department of Electronics Engineering, Ching-Yun University, Chungli, Taiwan 320;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117
Venue:
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Year:
2009

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Abstract

A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware implementation of C-means algorithm. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.