Research on Evaluation of Parallelization on an Embedded Multicore Platform

  • Authors:
  • Tao Liu;Zhenzhou Ji;Qing Wang;Dali Xiao;Shuyan Zhang

  • Affiliations:
  • School of Computer Science and Technology, Harbin Institute of Technology, Heilongjiang, China 150001;School of Computer Science and Technology, Harbin Institute of Technology, Heilongjiang, China 150001;School of Computer Science and Technology, Harbin Institute of Technology, Heilongjiang, China 150001;School of Computer Science and Technology, Harbin Institute of Technology, Heilongjiang, China 150001;School of Computer Science and Technology, Harbin Institute of Technology, Heilongjiang, China 150001

  • Venue:
  • APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
  • Year:
  • 2009

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Abstract

In order to solve the problem of serious performance bottleneck in traditional embedded platform, the parallelization of evaluation algorithms based on an embedded multicore platform is implemented. By analyzing the process of the parallel algorithms on the embedded chip multicore platform, and effectively using the limited memory and cache resource, the evaluation algorithms are implemented in an embedded multicore processor FPGA full function simulation platform. After comparing the parallelization effects of the two multithread models, a conclusion can be made that the shared memory model of parallel multithread fits the embedded multicore platform well. The parallel model generates substantial overall performance increase. An average relative speedup of 3.28 is achieved and meets the low memory resource in embedded architecture. And with the increase in core number the parallelization based on OpenMP model has shown good scalability.