Self-organization and associative memory: 3rd edition
Self-organization and associative memory: 3rd edition
Special Computer Architectures for Pattern Processing
Special Computer Architectures for Pattern Processing
Unifikationsgraphen für intelligentes Backtracking in Deduktionssystemen
GWAI '83 Proceedings of the 7th German Workshop on Artificial Intelligence
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An associative processor for theorem proving in first order logic is described. It is designed on the basis of the deduction plan method, introduced by Cox and Pietrzykowski. The main features of this method are the separation of unification from deduction and the incorporation of a method for intelligent backtracking. This kind of backtracking is based on a special unification procedure. An improved version of this unitization procedure is given, which outputs a unification graph with constraints. In the case of a unification conflict, sufficient information for a directed backtracking step can be gained from the unifiestion graph. According to the deduction plan method, the ASSIP-T memory consists of two parts, one for the deduction plan and the other for the unification graph. ASSIP-T can perform deduction and unification in parallel. Both memory parts consist of a set of subparts each of which keeps the information about clauses or terms, respectively. A subpart is a lineararray of cells provided with a control unit and can be regarded as a subprocessor.