Parallel adder with low costs and depth

  • Authors:

  • Alexander Gamkrelidze

  • Affiliations:

  • I. Javakhishvili Tbilisi State University, Department of Computer Science, Tbilisi, Georgia

  • Venue:
  • ECC'09 Proceedings of the 3rd international conference on European computing conference
  • Year:
  • 2009

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Abstract

In this paper we introduce a parallel algorithm for fast prefix computation. As a result, we construct a fast recursive and symmetric parallel adder with linear costs and time complexity T(AN) N + √2 ċ logN + 0.25 + 1.5. Compared to other known circuits it has better time complexity with the comparable (and sometimes better) area costs. Using the Pass Transistor Logic, we get a parallel adder with lower power consumption, linear costs and time complexity T(SN) = logN + 3.