High-performance multi-pattern matching structure in hardware network firewall

Authors:
Wang Jie;Ji Zhen-Zhou;Hu Ming-Zeng
Affiliations:
Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, Heilong, China;Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, Heilong, China;Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, Heilong, China
Venue:
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
Year:
2009

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Abstract

Along with development of network techniques and firewall techniques, multipattern matching for content filtering, virus detection and other network security measures is emphasized in the field of hardware firewall. Principles of multi-pattern matching on network firewall based on FPGA (Field Programmable Gate Array) are presented: low latency, supporting non-fixed-length pattern and forward matching. And architecture of high-performance matching on data link layer forming pipeline with frame transmission is proposed especially for multi-port scheduling. By academic analysis and experimental validation it can support applications of high-performance hardware network firewall and effectively reduce additional delays by expand logics.