Digital phase-locked loop and its realization

  • Authors:

  • Tsai-Sheng Kao;Sheng-Chih Chen;Yuan-Chang Chang;Sheng-Yun Hou;Chang-Jung Juan

  • Affiliations:

  • Department of Electronic Engineering, Hwa-Hsia Institute of Technology, Chung Ho, Taipei County, Taiwan, R.O.C.;ChengChi University, Taipei City, Taiwan, R.O.C.;Department of Electronic Engineering, Hwa-Hsia Institute of Technology, Chung Ho, Taipei County, Taiwan, R.O.C.;Department of Electronic Engineering, Hwa-Hsia Institute of Technology, Chung Ho, Taipei County, Taiwan, R.O.C.;Department of Electronic Engineering, Hwa-Hsia Institute of Technology, Chung Ho, Taipei County, Taiwan, R.O.C.

  • Venue:
  • AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
  • Year:
  • 2009

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Abstract

The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the DPLL system is first formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering.