Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions

  • Authors:

  • Garo Bournoutian;Alex Orailoglu

  • Affiliations:

  • University of California, San Diego, La Jolla, CA, USA;University of California, San Diego, La Jolla, CA, USA

  • Venue:
  • CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
  • Year:
  • 2009

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Abstract

Today, embedded processors are expected to be able to run complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. As such, the impact of memory latencies on the execution time increasingly becomes evident. All the while, it is also expected that embedded processors be power-conscientious as well as of minimal area impact. As a result, traditional methods for addressing performance and memory latencies, such as multiple issue, out-of-order execution and large, associative caches, are not aptly suited for the embedded domain due to the significant area and power overhead. This paper explores a novel approach to mitigating execution delays caused by memory latencies that would otherwise not be possible in a regular in-order, single-issue embedded processor without large, power-hungry constructs like a Reorder Buffer (ROB). The concept relies on both compile-time and run-time information to safely allow non-data-dependent instructions to continue executing while a memory stall has occurred. The simulation results show significant improvement in execution throughput of approximately 11%, while having a minimal impact on area overhead and power.