An event-based network-on-chip monitoring service
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at run time could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used and explained in our case study to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.12% performance improvement compared with the traditional stop-go method with 1.4% area overhead in an 8*8-core MPSoC in 45nm.