NoC-aware cache design for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Practically private: enabling high performance CMPs through compiler-assisted data classification
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Ordering circuit establishment in multiplane NoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
| Hi-index | 0.00 |
In Chip Multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design. Previously proposed techniques for reducing router latency using express virtual channels or hybrid circuit switching effectively reduce communication latency. However, our analysis of communication traffic of a suite of scientific and commercial workloads on a 16-core cache coherent CMP showed low utilization of circuits due to repeated establishment and tear down of circuits. In this paper, we explore circuit pinning, an efficient way of establishing circuits that promotes higher circuit utilization, adapts to changes in communication characteristics, simplifies network control, and allows smarter routing techniques due to the stability of configured circuits. Comparison with state of the art packet switched and hybrid circuit switched interconnects across different cache organizations demonstrates the benefits of our technique.