Connectivity Models for Optoelectronic Computing Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
Impact of the LSI on High-Speed Computer Packaging
IEEE Transactions on Computers
Information flow and interconnections in computing: extensions and applications of Rent's rule
Journal of Parallel and Distributed Computing
| Hi-index | 14.98 |
A key problem in the effective use of large-scale integration is the design and partitioning of computer logic to achieve sufficiently high circuit-to-pin ratios. In this paper a power-law relationship between pins and partitioned circuits is discussed and empirical evidence is presented that implies that the pin requirement is a sensitive function of the performance level of the logic. Two techniques for increasing the circuit-to-pin ratio are discussed. The first is to serialize the interchip transfer of information that results in a degradation in performance of the logic. The second is to encode the information to be transferred so that fewer pins are required but without reducing the performance. The results of experiments using the encoding principle to map a small logic graph onto chips are presented to obtain an indication of the effectiveness of this technique. It is shown that the relationship between circuits and pins when using encoding remains a power law.