A memory efficient FPGA implementation of quasi-cyclic LDPC decoder
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Which codes have cycle-free Tanner graphs?
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Design methods for irregular repeat-accumulate codes
IEEE Transactions on Information Theory
Turbo decoding as an instance of Pearl's “belief propagation” algorithm
IEEE Journal on Selected Areas in Communications
| Hi-index | 0.00 |
Repeat-Accumulate code has been widely used in various practical communication systems due to its special structure that can be encoded with a low complexity turbo-like encoder and decoded with a high-speed parallel algorithm. However, the construction of RA codes with large girth is still a challenging problem. In this paper, the girth upper bound of RA codes is analyzed and a novel RA code construction scheme is proposed. This scheme generates the parity-check matrix with superimposed structured interleavers, guaranteeing the resulting matrix to be globally optimized. Compared with the RA codes constructed with traditional structured interleavers such as π-rotation interleavers, pseudo-random interleavers, combinatorial interleavers, and modified L-type interleavers, the codes constructed with the proposed method exhibit better error-correcting performance. Moreover, a parallel VLSI codec architecture is proposed for the RA codes generated with the proposed method in this paper. Modifying the conventional RA encoder architecture, the codec for RA codes from our proposed method may have the same hardware implementation complexity as that for traditional RA codes, while the data throughput of our codec may achieve up to 450Mbps, which may be of great value for practical applications.