Efficient content analysis engine for visual surveillance network

Authors:
Wei-Kai Chan;Jing-Ying Chang;Tse-Wei Chen;Yu-Hsiang Tseng;Shao-Yi Chien
Affiliations:
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
2009

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Abstract

In the next-generation visual surveillance systems, content analysis tools will be integrated. In this paper, to accelerate these tools, it is proposed to integrate a hardware content analysis engine into a smart camera system-on-a-chip (SoC). A smart camera SoC hardware architecture with the proposed visual content analysis engine is first presented. This engine consists of dedicated accelerators and a programmable morphology coprocessor. Stream processing design concept, frame-level pipelining, and subword level parallelism are employed together to efficiently utilize the bandwidth of the system bus and achieve high throughput. The implementation results show that, with 168 K logic gates and 40.63 Kb on-chip memory, a processing speed of 30 640 × 480 frames/s can be achieved, while the operations of video object segmentation, object description and tracking, and face detection and scoring are supported.