Full RDO-support power-aware CABAC encoder with efficient context access

Authors:
Xiaohua Tian;Thinh M. Le;Xi Jiang;Yong Lian
Affiliations:
Department of Electrical and Computer Engineering, National University of Singapore, Singapore;Department of Electrical and Computer Engineering, National University of Singapore, Singapore;Department of Electrical and Computer Engineering, National University of Singapore, Singapore;Department of Electrical and Computer Engineering, National University of Singapore, Singapore
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
2009

Citing 5
Cited 0

On The Impact of Technology Scaling On Mixed PTL/Static Circuits

ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard

IEEE Transactions on Circuits and Systems for Video Technology
High-Throughput Architecture for H.264/AVC CABAC Compression System

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose a full-hardware context-based adaptive binary arithmetic coder (CABAC) encoder, which is the entropy coding tool adopted in the main and higher profiles of the video coding standard H.264/AVC. All CABAC coding features are implemented in hardware (HW), and different coding modes including rate-distortion optimization (RDO) are fully supported. An efficient memory access scheme is also proposed to reduce context RAM access frequency, context RAM size, and operation delay for RDO context state backup and restoration. Constant throughput of 1 bin per cycle is achieved in different coding configurations. The CABAC encoder is physically implemented in 0.13 µm process, and its post-layout simulation can be run at 328 MHz. The chip takes up 1.41 mm2, and dissipates 0.79 mW to support 720p60 HDTV real-time encoding in RDO-off mode. Compared to the state-of-the-art reference design, the most significant advantage of this design is that a full HW implementation of CABAC encoder is proposed, which minimizes the computation on the host processor and data transfer on the system bus. Power consumption is minimal compared to reference designs using the same technology.