Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding

  • Authors:
  • Peng Zhang;Don Xie;Wen Gao

  • Affiliations:
  • Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China and Graduate School of Chinese Academy of Sciences, Beijing, China;Spreadtrum Communication Inc., Beijing, China;Digital Media Institute, Peking University, Beijing, China

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents an efficient VLSI architecture for H.264/AVC content-adaptive binary arithmetic code (CABAC) decoding. We introduce several new techniques to maximize the parallelism of the decoding process, including variable-bin-rate strategy, multiple-bin arithmetic decoding, and efficient probability propagation scheme. The CABAC engine can ensure the real-time decoding for H.264/AVC main profile HD level 4.0. Synthesis results show that the multi-bin decoder can be operated up to 45 MHz, and the total logic area is only 42 K gates when targeted at TSMC's 0.18-µm process.