The Z-Coder Adaptive Binary Coder
DCC '98 Proceedings of the Conference on Data Compression
Optimal hardware and software arithmetic coding procedures for the Q-Coder
IBM Journal of Research and Development - Q-Coder adaptive binary arithmetic coder
IBM Journal of Research and Development
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
High-performance arithmetic coding VLSI macro for the H264 video compression standard
IEEE Transactions on Consumer Electronics
A high performance CABAC decoding architecture
IEEE Transactions on Consumer Electronics
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
Microprocessors & Microsystems
Joint Algorithm-Architecture Optimization of CABAC
Journal of Signal Processing Systems
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Journal of Signal Processing Systems
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This paper presents an efficient VLSI architecture for H.264/AVC content-adaptive binary arithmetic code (CABAC) decoding. We introduce several new techniques to maximize the parallelism of the decoding process, including variable-bin-rate strategy, multiple-bin arithmetic decoding, and efficient probability propagation scheme. The CABAC engine can ensure the real-time decoding for H.264/AVC main profile HD level 4.0. Synthesis results show that the multi-bin decoder can be operated up to 45 MHz, and the total logic area is only 42 K gates when targeted at TSMC's 0.18-µm process.