Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops

  • Authors:
  • Herminio Martínez;Eva Vidal;Eduard Alarcón;Alberto Poveda

  • Affiliations:
  • Department of Electronics Engineering, Technical University of Catalonia (EUETIB-UPC), Barcelona, Spain 08036;Department of Electronics Engineering, Technical University of Catalonia (UPC), Barcelona, Spain 08034;Department of Electronics Engineering, Technical University of Catalonia (UPC), Barcelona, Spain 08034;Department of Electronics Engineering, Technical University of Catalonia (UPC), Barcelona, Spain 08034

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2009

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Abstract

Continuous-time filters with automatic tuning loops are nonlinear feedback systems that are potentially unstable. To ensure stability, particularly if the design of the loop controllers is to be improved, the appropriate linear dynamic modeling of the tunable filter, including control inputs, should be attained. This work aims to present a general dynamic modeling of continuous-time analog filters with automatic tuning capability. The general analysis leads to an equivalent small-signal linearized incremental model, from which transfer functions between output variables and control voltages are obtained. Subsequent to the analysis, it is possible to design compensated loops with enhanced stability and dynamic performance. By way of example, the modeling of a particular band-pass CMOS continuous-time analog filter is presented in this paper. Two transfer functions are derived: the transfer function between the output phase shift and the central frequency control voltage, and that between the output amplitude and the quality factor control voltage. These functions are required to properly tune the central frequency and quality factor parameters. This modeling makes it possible to propose an adaptive controller with improved stability and a possible implementation for such a controller. Finally, experimental results are shown for a CMOS 0.8 μm technology.