A real-time hardware-software codesign technique of network protocols to provide QoS

Authors:
Taehoon Kim;Sungwoo Tak
Affiliations:
Pusan National University, Busan, South Korea;Pusan National University, Busan, South Korea
Venue:
Proceedings of the 2009 International Conference on Hybrid Information Technology
Year:
2009

Citing 8
Cited 0

Program Implementation Schemes for Hardware-Software Systems

Computer
Microc/OS-II

Microc/OS-II
Resource Management in Networked Multimedia Systems

Computer
TCP Onloading for Data Center Servers

Computer
A Switched Ethernet Protocol for Hard Real-Time Embedded System Applications

AINA '05 Proceedings of the 19th International Conference on Advanced Information Networking and Applications - Volume 2
Full TCP/IP for 8-bit architectures

Proceedings of the 1st international conference on Mobile systems, applications and services
An Open TCP/IP Core for Reconfigurable Logic

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Hardware/Software Partitioning Using Bayesian Belief Networks

IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present the inter-task communication technique incorporating the RHSCC (Real-time Hardware-Software Communcation Channel) that makes it possible to resolve the hardware-software co-design issue of implementing network protocols in the NoC (Network on Chip) architecture developed in this paper. We address this issue as a partition problem of implementing any network protocol suite into real-time application-specific and reconfigurable hardware and software tasks. Such a task decomposition technique can improve co-design productivity by supporting the modularity and reuse of complex network protocol cores. The RHSCC guarantees the real-time performance of periodic packets and minimize the average response time of aperiodic packets in order to provide the QoS support. A case study based on experiments is conducted to illustrate the application and efficiency of the proposed technique by implementing it in the NoC architecture derived from the Altera's Excalibur EPXA4 which is a commercial SoC (System on Chip) platform.