Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem
Communications of the ACM
Communications of the ACM
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In this paper, we propose a CQS (Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS (Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. We present a CQS (Calendar Queue Scheduler) architecture implemented in synthesizable Verilog form. We simulated the area for both each module and each memory. The area for each module is referenced by NAND(2x1) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). As the day size increases, the increment of the total area increases. According to the increase of the memory's entry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. Even though the CQS is eligible for rate control and delay control and it is in pursuit of home gateway corresponding to the end points of receiver on end-to-end QoS, its biggest problem is the increased memory size. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware. Also, its biggest problem on designing CQS is the memory size. We surely know that it is important to define the number of priorities and the day size for 1 year.