Digital radio systems on a chip: a systems approach
Digital radio systems on a chip: a systems approach
VERILOG Styles for Synthesis of Digital Systems
VERILOG Styles for Synthesis of Digital Systems
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In this paper, we develop an optimal hardware algorithm to perform smart diversity on a set of receive antenna array in a communication system to detect the RSSI in each antenna, and perform the algorithm to generate a selection signal for making an appropriate antenna switch. It bases on this selection signal to activate the combinational circuit to select its associated input signal, it then outputs this selected input signal for further measurement or test. Also, a test bench prepared with HDL language is used as the basic test platform that we can make input entry, configure algorithm, test and estimate the system performance. This developed algorithm improves the antenna selection performance compared to the conventional method, which follows some criteria to select from previous input signals the signal that has the largest RSSI. The index to measure the performance is termed as Success Rate and will be described later in more detail. We select Verilog as the HDL language, Modelsim as the RTL simulator and use Debussy for waveform analysis. The simulation platform is exercised on Windows-XP with Cygwin environment, which eventually emulates UNIX and/or LINUX systems. Therefore, the whole design can be also implemented on UNIX or LINUX system by simply moving the design package thereto.