High-throughput layered decoder implementation for quasi-cyclic LDPC codes

Authors:
Kai Zhang;Xinming Huang;Zhongfeng Wang
Affiliations:
Department of Electrical and Computer Engineering, Worcester Polytechnic Institute, Worcester, MA;Department of Electrical and Computer Engineering, Worcester Polytechnic Institute, Worcester, MA;Broadcom Corp., Irvine, CA
Venue:
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
Year:
2009

Citing 8
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Abstract

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2Gbps at 10 iterations. The operating frequency is 950MHz after synthesis and the chip area is 2.9mm2.