A configurable MIPS simulator for teaching computer architecture

• Authors: Muhammad Jahangir Ikram
• Venue: CATE '07 Proceedings of the 10th IASTED International Conference on Computers and Advanced Technology in Education
• Year: 2007

We present Visual-MIPS, a new tool for MIPS processor simulation, which adds a new dimension to teaching of computer architecture. Unlike many available tools for MIPS processor simulation such as SPIM [1], visual MIPS is fully configurable and can be used to teach subtle differences between processor architectures. There are a number of other tools that have been developed for simulating MIPS processor for education [2], [3] but they mainly focus on a fixed processor configuration. In the first experiment, single cycle configuration is used which allows study of processor behaviour for basic instructions as described in [4], [5]. For pipeline studies we have designed three experiments. In the first experiment, students study basic pipelined processor and discover problems with pipelining. Students are gradually asked to introduce hazard detection and forwarding logic. Next two experiments focus on branch hazards. By choosing different static branch strategies, e.g., flush pipeline, predict not taken, delayed branching and cancelled branching, they can write their own simple routines and run them on many different processor configurations. The real challenge has been the simulator to work correctly for all different configurations. This tool is especially useful for understanding and solving problems in course textbooks [4], [5].