Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
Rate-compatible puncturing of low-density parity-check codes
IEEE Transactions on Information Theory
Large-girth nonbinary QC-LDPC codes of various lengths
IEEE Transactions on Communications
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This paper describes and analyzes low-density parity-check code families that support variety of different rates while maintaining the same fundamental decoder architecture. Such families facilitate the decoding hardware design and implementation for applications that require communication at different rates, for example to adapt to changing channel conditions. Combining rows of the lowest-rate parity-check matrix produces the parity-check matrices for higher rates. An important advantage of this approach is that all effective code rates have the same blocklength. This approach is compatible with well known techniques that allow low-complexity encoding and parallel decoding of these LDPC codes. This technique also allows the design of programmable analog LDPC decoders. The proposed design method maintains good graphical properties and hence low error floors for all rates.