Toward low LDPC-code floors: a case study
IEEE Transactions on Communications
On the BCJR trellis for linear block codes
IEEE Transactions on Information Theory
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
Asymptotic Spectra of Trapping Sets in Regular and Irregular LDPC Code Ensembles
IEEE Transactions on Information Theory
Construction of Regular and Irregular LDPC Codes: Geometry Decomposition and Masking
IEEE Transactions on Information Theory
Low-floor detection/decoding of LDPC-coded partial response channels
IEEE Journal on Selected Areas in Communications
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One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code's Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than floors of the the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.