Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Detection of Signals in Noise
Telecommunication Systems Engineering
Telecommunication Systems Engineering
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Carrier phase and frequency estimation for pilot-symbol assisted transmission: bounds and algorithms
IEEE Transactions on Signal Processing
SNR estimation for nonconstant modulus constellations
IEEE Transactions on Signal Processing
IEEE Transactions on Wireless Communications
Maximum-likelihood estimation of phase and frequency of MPSK signals
IEEE Transactions on Information Theory
Rayleigh fading channels in mobile digital communication systems. I. Characterization
IEEE Communications Magazine
Rayleigh Fading Channels in Mobile Digital Communication Systems Part II: Mitigation
IEEE Communications Magazine
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In this paper we present two new Non Data Aided (NDA) phase detectors (PDs) for carrier synchronization Phase Locked Loops (PLLs) in M-ary Phase Shift Keying (M-PSK) receivers. The first structure is a self-normalizing modification of the M-th order nonlinearity detector. We investigate this detector theoretically in order to predict its S-curve, self-noise, squaring-loss, and phase-error variance performance. These theoretical predictions are then verified by computer simulations, and the results are contrasted with results obtained using other NDA and Decision Directed (DD) phase detectors. As those comparisons show, the proposed structure offers improved phase-error variance performance that is robust to Automatic Gain Control (AGC) circuit imperfections. Moreover, the new detector has a compact hardware structure suitable for implementation within an FPGA or ASIC. The second phase detector structure presented is an adaptive detector whose principal novelty is that it dynamically adapts the phase detector's gain to allow the PLL to perform optimally at any input Signal-to-Noise Ratio (SNR) at which it can lock. This detector is also robust vis-à-vis the AGC and has a compact hardware implementation suitable for FPGAs and ASICs.