Practical loss-resilient codes
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Optimizing the Mapping of Low-Density Parity Check Codes on Parallel Decoding Architectures
ITCC '01 Proceedings of the International Conference on Information Technology: Coding and Computing
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
Finite-length analysis of low-density parity-check codes on the binary erasure channel
IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices
IEEE Transactions on Information Theory
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
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This paper presents a general procedure for designing low density parity check (LDPC) codes for multiprocessor software defined radio platforms. Our approach is to design the LDPC code to match the constraints imposed by the hardware architecture, without compromising on the communication performance. The proposed architecture-aware code design procedure involves feature identification, code construction and verification. We demonstrate the effectiveness of our procedure for three cases. If the local memory of the processor is small and it can only process one horizontally partitioned submatrix at a time, we show how the code can be constructed so that the traffic to the global memories is reduced by 2X. If the row weight of the matrix is large and each processor processes a vertically partitioned submatrix, we show how the matrix can be constructed so that the computational load is evenly distributed among the processors. If the processors have no storage capability and all data is stored in global memories, then for the case when all traffic is through a multistage interconnection network, we show how code construction can be used to significantly reduce the number of routing conflicts. In all three cases, the resulting LDPC codes can not only be mapped efficiently onto the multiprocessor platform but also have very good frame error performance.