Performance evaluation of NEC SX-9 using real science and engineering applications

  • Authors:
  • Takashi Soga;Akihiro Musa;Youichi Shimomura;Ryusuke Egawa;Ken'ichi Itakura;Hiroyuki Takizawa;Koki Okabe;Hiroaki Kobayashi

  • Affiliations:
  • Tohoku University and NEC System technologies;NEC Corporation;NEC Software Tohoku;Tohoku University;Japan Agency for Marine-Earth Science and Technology;Tohoku University;Tohoku University;Tohoku University

  • Venue:
  • Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper describes a new-generation vector parallel supercomputer, NEC SX-9 system. The SX-9 processor has an outstanding core to achieve over 100Gflop/s, and a software-controllable on-chip cache to keep the high ratio of the memory bandwidth to the floating-point operation rate. Moreover, its large SMP nodes of 16 vector processors with 1.6Tflop/s performance and 1TB memory are connected with dedicated network switches, which can achieve inter-node communication at 128GB/s per direction. The sustained performance of the SX-9 processor is evaluated using six practical applications in comparison with conventional vector processors and the latest scalar processor such as Nehalem-EP. Based on the results, this paper discusses the performance tuning strategies for new-generation vector systems. An SX-9 system of 16 nodes is also evaluated by using the HPC challenge benchmark suite and a CFD code. Those evaluation results clarify the highest sustained performance and scalability of the SX-9 system.