Distributing SystemC structures in parallel simulations

  • Authors:
  • V. Galiano;H. Migallón;D. Pérez-Caparrós;M. Martínez

  • Affiliations:
  • University Miguel Hernández of Elche, Elche, Alicante, Spain;University Miguel Hernández of Elche, Elche, Alicante, Spain;University Miguel Hernández of Elche, Elche, Alicante, Spain;Design of Systems on Silicon (DS2), C. R. Darwin, Paterna Valencia, Spain

  • Venue:
  • SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
  • Year:
  • 2009

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Abstract

This paper deals with the most popular attempts of distributing SystemC simulations. SystemC is becoming a popular framework for System-On-Chip (SoC) design and verification. Innovation in processor design does not come easily. Smaller features, faster speeds, and intricate digital logic require more simulation resources to accurately gauge the worth of a new design. In order to provide these resources, distributed simulation conforms to a scalable solution to test and verification of complex system models. In this paper, we review the main approaches to distribute SystemC framework. We analyze the efficiency of the main approaches to distribute the simulation of SystemC models and we present our own approach, which is based on the analyzed ones. We test the scalability of our distributed approach by increasing the number of elements in a self-developed system model. After this, we evaluate its usability in a real SystemC design where complex C++ structures are used and must be distributed across several processes. We show the effectiveness of our approach using a model with n RISC processors and a single n-port RAM.