A digital PLL with a stochastic time-to-digital converter

Authors:
Volodymyr Kratyuk;Pavan Kumar Hanumolu;Kerem Ok;Un-Ku Moon;Kartikeya Mayaram
Affiliations:
Silicon Laboratories Inc., Beaverton, OR and School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR;School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR;MaxLinear Inc., Carlsbad, CA and School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR;School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR;School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Year:
2009

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Abstract

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-µm CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.