CMOS VCOs for frequency synthesis in wireless biotelemetry
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Analysis and Design of Integrated Circuits
Analysis and Design of Integrated Circuits
A switching-based phase noise model for CMOS ring oscillators based on multiple thresholds crossing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents new theoretical results on the phase noise of a class of unsaturated ring oscillators. These new results focus on cycle-to-cycle correlation as a source of timing jitter and highlight its importance in contributing to the phase noise of these unsaturated ring oscillators. Because the outputs of saturated ring oscillators always reach the power supply, such cycle-to-cycle correlation is not present there. This paper presents an in-depth treatment of the two-stage implementation of these unsaturated ring oscillators. It is shown that the timing jitter of each quarter period of this implementation follows an autoregressive process. The results also include a closed-form solution for the power spectral density of the phase noise in terms of circuit parameters such as transistor sizing and bias currents, thus providing new design insights. Using this solution, this paper shows that, under a proper choice of circuit parameters, the phase noise can improve by up to 20 dBc/Hz. Simulations which verify the dependence of timing jitter on cycle-to-cycle correlation and also the 20-dBc/Hz improvement are performed.