Simulation and analysis of random decision errors in clocked comparators

Authors:
Jaeha Kim;Brian S. Leibowitz;Jihong Ren;Chris J. Madden
Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA and Rambus, Inc., Los Altos, CA;Rambus, Inc., Los Altos, CA;Rambus, Inc., Los Altos, CA;Rambus, Inc., Los Altos, CA
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Year:
2009

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Abstract

Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor γ = 2.