Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
Proceedings of the 42nd annual Design Automation Conference
Nonuniform linear regression with block-wise sample-minimum preprocessing
IEEE Transactions on Signal Processing
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One of the factors limiting the performance of continuous-time sigma-delta modulators (CTSDMs) is clock jitter. This jitter can be classified as synchronous and accumulated/long-term jitter. A clock that is derived from a phase-lock loop contains both types of jitter. In this paper, we present a framework that can be used to obtain the output spectrum in the presence of jitter, either synchronous or accumulated or a combination of both. First, a general expression for the output power spectral density (PSD) of the CTSDM in the presence of clock jitter is derived. Based on this, analytical expressions for the output PSD are obtained for particular cases of synchronous and long-term jitter. These are validated against behavioral simulations.