Algorithm level evaluation of cryptosystem resistance to second-order DPA

  • Authors:
  • Akihiko Sasaki;Kôki Abe

  • Affiliations:
  • The University of Electro-Communications, Chofugaoka Chofu-shi, Tokyo, Japan;The University of Electro-Communications, Chofugaoka Chofu-shi, Tokyo, Japan

  • Venue:
  • CNIS '07 Proceedings of the Fourth IASTED International Conference on Communication, Network and Information Security
  • Year:
  • 2007

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Abstract

In a previous study, we verified by simulation at the transistor level that the difference in power consumptions in Differential Power Analysis (DPA) can be approximated by using the Hamming weight of the bit string that includes an attacked bit position. Based on that verification, we proposed an algorithm-level method for evaluating the resistance of cryptosystems to DPA attacks and demonstrated the effectiveness of the method by applying it to a first-order DPA-resistance evaluation of Data Encryption Standard (DES) implementations. In this paper, we apply this method to second-order DPA and show that the simulation results are consistent with the experimental results of attacks against a smartcard. We also show that using the simulation method we can quantitatively evaluate the resistance of the DES algorithm and its countermeasures to second-order DPA. This method is faster than other methods used at the RTL and downstream levels and is useful for quantitatively evaluating the resistance of countermeasures to DPA at the upstream level of cryptosystem design.