A new approach to the functional design of a digital computer
IRE-AIEE-ACM '61 (Western) Papers presented at the May 9-11, 1961, western joint IRE-AIEE-ACM computer conference
A Database Perspective on Building Large Applications - Experience Report
EDBT '00 Proceedings of the 7th International Conference on Extending Database Technology: Advances in Database Technology
On the design of Always Compatible Instruction Set Architecture(ACISA)
ACM SIGARCH Computer Architecture News
Check Schemes for Integrated Microprogrammed Control and Data Transfer Circuitry
IEEE Transactions on Computers
The design of transformer (Dimond ring) read-only stores
IBM Journal of Research and Development
Autonomous learning of load and traffic patterns to improve cluster utilization
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Decimal floating-point support on the IBM system z10 processor
IBM Journal of Research and Development
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Interpreting “systems architecting”
Systems Engineering
A classification of middleware to support virtual machines adaptability in IaaS
Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware
Hi-index | 0.02 |
The architecture* of the newly announced IBM System/360 features four innovations: 1. An approach to storage which permits and exploits very large capacities, hierarchies of speeds, readonly storage for microprogram control, flexible storage protection, and simple program relocation. 2. An input/output system offering new degrees of concurrent operation, compatible channel operation, data rates approaching 5,000,000 characters/second, integrated design of hardware and software, a new low-cost, multiple-channel package sharing main-frame hardware, new provisions for device status information, and a standard channel interface between central processing unit and input/output devices. 3. A truly general-purpose machine organization offering new supervisory facilities, powerful logical processing operations, and a wide variety of data formats. 4. Strict upward and downward machine-language compatibility over a line of six models having a performance range factor of 50. This paper discusses in detail the objectives of the design and the rationale for the main features of the architecture. Emphasis is given to the problems raised by the need for compatibility among central processing units of various size and by the conflicting demands of commercial, scientific, real-time, and logical information processing. A tabular summary of the architecture is shown in the Appendices.