Hardware implementation of a modified delay-coordinate mapping-based QRS complex detection algorithm
EURASIP Journal on Applied Signal Processing
A patient-adaptive profiling scheme for ECG beat classification
IEEE Transactions on Information Technology in Biomedicine
An improved procedure for detection of heart arrhythmias with novel pre-processing techniques
Expert Systems: The Journal of Knowledge Engineering
Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs
Digital Signal Processing
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The aim of this paper is to present an FPGA-oriented system design for ECG signal processing. The system performs QRS complex detection and beat classification into either normal or premature ventricular contractions. QRS complex detection is made with an algorithm based on a phase-space portrait of an ECG signal, while for beat classification a part of the Open Source ECG Analysis Software is used. The former is performed in HW and the latter in SW on an integrated PowerPC 405 core. The algorithm was developed on the MIT-BIH Arrhythmia Database where a QRS complex sensitivity of 99.82% and positive predictivity of 99.83% and a PVC sensitivity of 92.36% and specificity of 95.54% were achieved. The processing speed is measured and the results show that the HW/SW implementation of the algorithm processes the ECG data up to 15 times faster than the SW implementation, meaning that real-time ECG signal analysis is possible at much lower frequencies than in analysis performed in SW. We show that the HW/SW implementation makes it possible to use low-cost FPGA devices with soft-core microprocessors in systems where a high processing speed is required.