The SGI Origin: a ccNUMA highly scalable server
Proceedings of the 24th annual international symposium on Computer architecture
Designing and evaluating a cost-effective optical network for multiprocessors
Journal of Parallel and Distributed Computing
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
WildFire: A Scalable Path for SMPs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Merging, sorting and matrix operations on the SOME-bus multiprocessor architecture
Future Generation Computer Systems - Special issue: Advanced services for clusters and internet computing
An Evaluation of the Oak Ridge National Laboratory Cray XT3
International Journal of High Performance Computing Applications
Selecting the right MBA schools - An application of self-organizing map networks
Expert Systems with Applications: An International Journal
A case study of applying LRFM model in market segmentation of a children's dental clinic
Expert Systems with Applications: An International Journal
Hi-index | 12.05 |
Broadcast-based DSM multiprocessors are nowadays an attractive platform for parallel computing due to their advantages in terms of scalability and programmability. In order to obtain high performance out of these systems, network latency reduction techniques should be developed, which requires the knowledge of the relationship between latency and other important DSM parameters. In this paper, self organizing maps (SOM) are used to investigate the effect of DSM parameters on network latency for a multiprocessor architecture interconnected by the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus). An event-based discrete simulator using OPNET Modeler is developed for simulating a SOME-Bus system containing 64-nodes. Two thousand data points have been collected in order to create the dataset used in this study. 2-dimensional (2D) maps are produced by using SOM to display the relationship between network latency and other parameters such as the miss rate to a modified block (P"m), fraction of write misses (P"w), probability of having an upgrade ownership request message (P"u"o"r), probability of having a cache full (P"c"f) and ratio of the mean thread run time to mean message transfer time (T/R). The results show that the most dominant DSM parameter effecting network latency is T/R, while P"c"f has the minimum affect on network latency among other parameters. The individual effect of P"m, P"w and P"u"o"r on network latency depends on the values of all other parameters.