Design of 600 Mbps MIMO wireless LAN system using GLST coding and its FPGA implementation

  • Authors:

  • W. A. Syafei;Y. Nagao;R. Imashioya;M. Kurosaki;B. Sai;H. Ochi

  • Affiliations:

  • Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan and Radrix Co., Ltd., Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan and Radrix Co., Ltd., Japan

  • Venue:
  • RWS'09 Proceedings of the 4th international conference on Radio and wireless symposium
  • Year:
  • 2009

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Abstract

In this paper we report our works on designing MIMO wireless LAN system with throughput 600 Mbps for 30 meter propagation range by using Generalized Layered Space Time (GLST) coding and its implementation on field programmable gate array (FPGA) chips. At the receiver we employ our low-complexity GLST decoder to maintain error performance with low computational complexity. A novel packet format is developed that allows compatibility with the IEEE 802.11 a/n system. Our system works on 5,25 GHz carrier frequency with 80 MHz bandwidth, uses 4 transmit antennas and 2 receive antennas and gives superior performance on channel model B TGn. The Register Transfer Level results show that the developed system is synthesized succesfully as well as the implementation on the target FPGA chips.