A low-power and wide tuning range frequency locked loop for a cognitive radio system

  • Authors:

  • Su Cui;Venkatesh Acharya;Bhaskar Banerjee

  • Affiliations:

  • Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX;Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX;Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX

  • Venue:
  • RWS'09 Proceedings of the 4th international conference on Radio and wireless symposium
  • Year:
  • 2009

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Abstract

We present a frequency locked loop with a novel frequency detector scheme that can be used in a phase locked loop for aided acquisition and reduces the locking time without increasing the loop bandwidth. This FLL scheme utilizes a novel frequency detector and negativeimpedance converter acting as a current conveyor without using an op-amp. The clock is generated by a simple three stage ring voltage-controlled oscillator (VCO) and a reference clock is sensed by two frequency detectors and converted to currents that are proportional to the frequency. These two currents adjust the supply voltage of the VCO. It shows a good tuning linearity over the range of 200 MHz - 600 MHz with a maximum power consumption of 1. 72mW at IGHz in TSMC 0.18 µm standard CMOS Technology. The settling time of the FLL is 105 ns. The FLL can be used to develop multi-standard frequency synthesizers for cognitive radio applications.