8K-point pipelined FFT/IFFT with compact memory for DVB-T using block floating-point scaling technique

  • Authors:

  • Hui-Gon Kim;Ki-Tae Yoon;Jin-Sun Youn;Jun-Rim Choi

  • Affiliations:

  • School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea;School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea;School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea;School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea

  • Venue:
  • ISWPC'09 Proceedings of the 4th international conference on Wireless pervasive computing
  • Year:
  • 2009

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Abstract

We Propose a 2K/4K/8K point FFT (Fast Fourier Transform) for OFDM (Orthogonal Frequency Division Multiplexing) of DVB-H (Digital Video Broadcast Terrestrial) Receiver. The proposed FFT architecture utilizes cascaded radix-4 single path feedback (SDF) structure based on the Radix-2/Radix-4 FFT algorithm. [11] We use block floating point scaling technique in order to increase SQNR. The 2K/8K FFT consists of 5 cascaded stages of radix-4 and 3 stages of radix-2 butterfly units. The SQNR of 58dB is achieved with 10-bit data input, 14-bit internal data and twiddle factors, and 18-bit data output. The core has 75,804 gates with 204,672 bits of RAM and 33,572 bits of ROM using 0.18µm CMOS technology.