IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing

Authors:
Tobias Schumacher;Christian Plessl;Marco Platzner
Affiliations:
-;-;-
Venue:
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Year:
2009

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FPGA acceleration of communication-bound streaming applications: architecture modeling and a 3D image compositing case study

International Journal of Reconfigurable Computing
IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators

Microprocessors & Microsystems

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Abstract

Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for ﬂexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we introduce the IMORC architectural template and the on-chip interconnect and demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XtremeData XD1000 reconfigurable computing system.