Bitonic sort on a chained-cubic tree interconnection network
Journal of Parallel and Distributed Computing
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The performance of a hardware/software architecture designed to perform a wide range of fast image processing tasks is evaluated and presented in this paper. The system architecture is based on Field Programmable Gate Array (FPGA) featuring soft-core processor MicroBlaze core processor and an external median filter co-processor using bitonic sort. The FPGA is based on a Xilinx Virtex-II Pro chip and is designed as a system on a programmable chip with the help of Embedded Design Kit. The system integrates the MicroBlaze, external and on chip memory, and median filter appropriate for the evaluation of the system performance. By using the median filter co-processor, the result shows that the process speed can be accelerated more than 10X. And resources occupied are given.