Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures
On the scalability and dynamic load-balancing of optimistic gate level simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Multi-State Q-Learning Approach for the Dynamic Load Balancing of Time Warp
PADS '10 Proceedings of the 2010 IEEE Workshop on Principles of Advanced and Distributed Simulation
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As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this paper, we examine the performance of a parallel Verilog simulator on four large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. We develop a parser for Verilog files enabling us to simulate in parallel all synthesizable Verilog circuits. We utilize four circuits as our test benches; the LEON Processor with 200k gates, the OpenSparc T2 processor with 400k gates and two Viterbi decoder circuits with 100k and 800k gates respectively. The simulator makes use of XTW and to our knowledge is the first Verilog simulator which can parse all synthesizable Verilog files. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. The simulators’ performance was shown to be scalable.