Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays

  • Authors:
  • N. Lopez-Benitez;J. A. B. Fortes

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1992

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Abstract

A method for the generation of detailed models of fault-tolerant processor arrays, based on stochastic Petri nets (SPNs), is presented. A compact SPN model of the array associates with each transition a set of attributes that includes a discrete probability distribution. Depending on the type of component and the reconfiguration scheme, these probabilities are determined using simulation or closed-form expressions and correspond to the survival of the array given that a number of components required by the reconfiguration process are faulty.