Efficient High-Level Power Estimation for Multi-standard Wireless Systems
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A GA-based design space exploration framework for parameterized system-on-a-chip platforms
IEEE Transactions on Evolutionary Computation
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Today there is a need for high performance chips that can provide very low power consumption, yet can operate over a number of application standards, such as operating a number of telecommunication standards depending on which country the device is in. This paper presents a new framework to enable the design of flexible systems by incorporating different range of reconfigurability in an embedded platform within an SOC design automatically. The SOC design automation involves identifying the best architectural features for the SOC platform, the configuration setting of reconfigurable cores, the type of interconnection schemes, their associated parameters such as data bandwidth, and placement of embedded cores in the communication infrastructures. For this optimization problem, a two-stage multi-objective optimization algorithm is presented. A multi-standard wireless telecommunication protocol is used to demonstrate our optimized designs in terms of area, power and performance.